29 research outputs found
Reliable Software for Unreliable Hardware - A Cross-Layer Approach
A novel cross-layer reliability analysis, modeling, and optimization approach is proposed in this thesis that leverages multiple layers in the system design abstraction (i.e. hardware, compiler, system software, and application program) to exploit the available reliability enhancing potential at each system layer and to exchange this information across multiple system layers
XBioSiP: A Methodology for Approximate Bio-Signal Processing at the Edge
Bio-signals exhibit high redundancy, and the algorithms for their processing
are inherently error resilient. This property can be leveraged to improve the
energy-efficiency of IoT-Edge (wearables) through the emerging trend of
approximate computing. This paper presents XBioSiP, a novel methodology for
approximate bio-signal processing that employs two quality evaluation stages,
during the pre-processing and bio-signal processing stages, to determine the
approximation parameters. It thereby achieves high energy savings while
satisfying the user-determined quality constraint. Our methodology achieves, up
to 19x and 22x reduction in the energy consumption of a QRS peak detection
algorithm for 0% and <1% loss in peak detection accuracy, respectively.Comment: Accepted for publication at the Design Automation Conference 2019
(DAC'19), Las Vegas, Nevada, US
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Reliable and resilient AI and IoT-based personalised healthcare services: A survey
Recent technological (e.g., IoT, 5G), and economic (e.g., UN 2030 Sustainable Development Goals) developments have transformed the healthcare sector towards more personalized and IoT-based healthcare services. These services are realized through control and monitoring applications that are typically developed using artificial intelligence (AI)/machine learning (ML) based algorithms, that play a significant role to highlight the efficiency of traditional healthcare systems. Current personalized healthcare services are dedicated in a specific environment to support technological personalization (e.g., personalized gadgets/devices). However, they are unable to consider different inter-related health conditions, leading to inappropriate diagnosis and affect sustainability and the long-term health/life of patients. Towards this problem, the state-of-the-art Healthcare 5.0 technology has evolved that supersede previous healthcare technologies. The goal of healthcare 5.0 is to achieve a fully autonomous healthcare service, that takes into account the interdependent effect of different health conditions of a patient. This paper conducts a comprehensive survey on personalized healthcare services. In particular, we first present an overview of key requirements of comprehensive personalized healthcare services (CPHS) in modern healthcare Internet of Things (HIoT), including the definition of personalization and an example use case scenario as a representative for modern HIoT. Second, we explored a fundamental three-layer architecture for IoT-based healthcare systems using both AI and non-AI-based approaches, considering key requirements for CPHS followed by their strengths and weaknesses in the frame of personalized healthcare services. Third, we highlighted different security threats against each layer of IoT architecture along with the possible AI and non-AI-based solutions. Finally, we propose a methodology to develop reliable, resilient, and personalized healthcare services that address the identified weaknesses of existing approaches
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis
Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging
Non-Volatile Memory (NVM) technology that has garnered attention to overcome
the drawbacks of conventional CMOS-based technologies. However, such
technologies must be evaluated before deployment under real workloads and
architecture. But there is a lack of available open-source STT-RAM-based system
evaluation framework, which hampers research and experimentation and impacts
the adoption of STT- RAM in a system. This paper proposes a novel, extendable
STT-RAM memory controller design integrated inside the gem5 simulator. Our
framework enables understanding various aspects of STT-RAM, i.e., power, delay,
clock cycles, energy, and system throughput. We will open-source our HOPE
framework, which will fuel research and aid in accelerating the development of
future system architectures based on STT-RAM. It will also facilitate the user
for further tool enhancement
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators
Multiplication is one of the widely used arithmetic operations in a variety of applications, such as image/video processing and machine learning. FPGA vendors provide high-performance multipliers in the form of DSP blocks. These multipliers are not only limited in number and have fixed locations on FPGAs but can also create additional routing delays and may prove inefficient for smaller bit-width multiplications. Therefore, FPGA vendors additionally provide optimized soft IP cores for multiplication. However, in this work, we advocate that these soft multiplier IP cores for FPGAs still need better designs to provide high-performance and resource efficiency. Toward this, we present generic area-optimized, low-latency accurate, and approximate softcore multiplier architectures, which exploit the underlying architectural features of FPGAs, i.e., lookup table (LUT) structures and fast-carry chains to reduce the overall critical path delay (CPD) and resource utilization of multipliers. Compared to Xilinx multiplier LogiCORE IP, our proposed unsigned and signed accurate architecture provides up to 25% and 53% reduction in LUT utilization, respectively, for different sizes of multipliers. Moreover, with our unsigned approximate multiplier architectures, a reduction of up to 51% in the CPD can be achieved with an insignificant loss in output accuracy when compared with the LogiCORE IP. For illustration, we have deployed the proposed multiplier architecture in accelerators used in image and video applications, and evaluated them for area and performance gains. Our library of accurate and approximate multipliers is opensource and available online at https://cfaed.tu-dresden.de/pd-downloads to fuel further research and development in this area, facilitate reproducible research, and thereby enabling a new research direction for the FPGA community
QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks
Adversarial examples have emerged as a significant threat to machine learning
algorithms, especially to the convolutional neural networks (CNNs). In this
paper, we propose two quantization-based defense mechanisms, Constant
Quantization (CQ) and Trainable Quantization (TQ), to increase the robustness
of CNNs against adversarial examples. CQ quantizes input pixel intensities
based on a "fixed" number of quantization levels, while in TQ, the quantization
levels are "iteratively learned during the training phase", thereby providing a
stronger defense mechanism. We apply the proposed techniques on undefended CNNs
against different state-of-the-art adversarial attacks from the open-source
\textit{Cleverhans} library. The experimental results demonstrate 50%-96% and
10%-50% increase in the classification accuracy of the perturbed images
generated from the MNIST and the CIFAR-10 datasets, respectively, on commonly
used CNN (Conv2D(64, 8x8) - Conv2D(128, 6x6) - Conv2D(128, 5x5) - Dense(10) -
Softmax()) available in \textit{Cleverhans} library
Security for Machine Learning-based Systems: Attacks and Challenges during Training and Inference
The exponential increase in dependencies between the cyber and physical world
leads to an enormous amount of data which must be efficiently processed and
stored. Therefore, computing paradigms are evolving towards machine learning
(ML)-based systems because of their ability to efficiently and accurately
process the enormous amount of data. Although ML-based solutions address the
efficient computing requirements of big data, they introduce (new) security
vulnerabilities into the systems, which cannot be addressed by traditional
monitoring-based security measures. Therefore, this paper first presents a
brief overview of various security threats in machine learning, their
respective threat models and associated research challenges to develop robust
security measures. To illustrate the security vulnerabilities of ML during
training, inferencing and hardware implementation, we demonstrate some key
security threats on ML using LeNet and VGGNet for MNIST and German Traffic Sign
Recognition Benchmarks (GTSRB), respectively. Moreover, based on the security
analysis of ML-training, we also propose an attack that has a very less impact
on the inference accuracy. Towards the end, we highlight the associated
research challenges in developing security measures and provide a brief
overview of the techniques used to mitigate such security threats